1. Field of the Invention
The present invention relates generally to power saving and, in particular, to clock gating for double data rate logic.
2. Background Art
A primary driver in the increase in computational power of modern integrated circuits is the ability to fit an increasing number of transistors in smaller and smaller areas. However, as the number of transistors increase, and therefore the number of circuits being switched, the power consumption of these circuits also increases.
One area of interest for power reduction research is the clock. In systems that have been modularly designed, clock gating can be used to stop supplying the clock to portions of the circuit that are not currently being used. For example, execution of an instruction may involve the use of one of several processing units, such as a floating point unit (“FPU”) or arithmetic logic unit (“ALU”).
A typical instruction may have need of only either the FPU or the ALU. If the instruction is being processed by the ALU, however, the FPU will still perform some manner of work, even though the result may not be needed. A solution is to use clock gating to disable the FPU during the relevant time interval, preventing the FPU from performing any computations and thereby wasting power.
However, existing clock gating solutions only operate on single data rate (“SDR”) logic, rather than on double data rate (“DDR”) logic. Accordingly, what is desired is systems and methods that provide the efficiencies of clock gating on DDR logic.